DS1371U+C01【PDF 2/15 页】IC BINARY COUNTER 32-BIT 8-USOP

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DS1371

10 of 15

Special Purpose Registers

The DS1371 has two additional registers (07h–08h) that control the WD/

ALM counter, square-wave

output, and interrupts.

Control Register (07h)

Bit #

Name

EOSC

WACE

WD/

ALM

INTCN

RS2

RS1

AIE

Default

Bit 7: Enable Oscillator (

EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the

oscillator is stopped. When this bit is set to a logic 1, the oscillator is stopped and the DS1371 is placed

into a low-power standby mode (IDDR). This bit is clear (logic 0) when power is first applied.

Bit 6: WD/

ALM Counter Enable (WACE). When set to logic 1, the WD/ALM counter is enabled.

When set to logic 0, the WD/

ALM counter is disabled, and the 24-bits can be used as general-purpose

RAM. This bit is clear (logic 0) when power is first applied.

Bit 5: WD/

ALM Counter Select (WD/ALM). When set to logic 0, the counter decrements every second

until it reaches 0 and is then reloaded and restarted. When set to logic 1, the WD/

ALM counter

decrements every 1/4096 of a second (approximately every 244μs) until it reaches 0, sets the AF bit in the

status register, and stops. If any of the WD/

ALM counter registers are read or written, or a rising edge on

the WDS pin occurs before the counter reaches 0, the counter is reloaded and restarted. This bit is clear

(logic 0) when power is first applied.

Bit 3: Interrupt Control (INTCN). This bit controls the SQW/

INT signal. When the INTCN bit is set to

logic 0, a square wave is output on the SQW/

INT pin whose frequency is defined by bits RS2 and RS1.

The oscillator must also be enabled for the square wave to be output. When the INTCN bit is set to logic

1, then this permits the alarm flag bit in the status register to assert SQW/

INT (provided that the alarm is

also enabled). The alarm flag is always set, regardless of the state of the INTCN bit. The INTCN bit is set

to logic 0 when power is first applied.

Bits 2 and 1: Rate Select 1 and 2 (RS2 and RS1). These bits control the frequency of the square-wave

output when the square wave has been enabled. Table 3 shows the square-wave frequencies that can be

selected with the RS bits. These bits are both set (logic 1) when power is first applied.

Bit 0: Alarm Interrupt Enable (AIE). When set to logic 1, this bit permits the AF bit in the status

INT (when INTCN = 1). When set to logic 0 or INTCN is set to logic 0, the AF bit

does not initiate the SQW/

INT signal. If the WD/ALM bit is set to a logic 1 and the AF flag is set, writing

AIE to a 0 does not truncate the 250ms pulse on the SQW/

INT pin. The AIE bit is at logic 0 when power

is first applied.

Table 3. SQW/

INT Operating Modes

WACE

WD/

ALM

INTCN

AIE

RS2

RS1

SQW/

INT OUTPUT

1Hz

4.096kHz

8.192kHz

32.768kHz

Alarm

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